diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index 40b98db..244ea49 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -45,54 +45,12 @@
 	return NULL;
 }
 
-/* DRAM init code ... */
-
-#define MV_SIP_DRAM_SIZE	0x82000010
-
-static u64 a8k_dram_scan_ap_sz(void)
-{
-	struct pt_regs pregs;
-
-	pregs.regs[0] = MV_SIP_DRAM_SIZE;
-	pregs.regs[1] = SOC_REGS_PHY_BASE;
-	smc_call(&pregs);
-
-	return pregs.regs[0];
-}
-
-static void a8k_dram_init_banksize(void)
-{
-	/*
-	 * The firmware (ATF) leaves a 1G whole above the 3G mark for IO
-	 * devices. Higher RAM is mapped at 4G.
-	 *
-	 * Config 2 DRAM banks:
-	 * Bank 0 - max size 4G - 1G
-	 * Bank 1 - ram size - 4G + 1G
-	 */
-	phys_size_t max_bank0_size = SZ_4G - SZ_1G;
-
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size <= max_bank0_size) {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-		return;
-	}
-
-	gd->bd->bi_dram[0].size = max_bank0_size;
-	if (CONFIG_NR_DRAM_BANKS > 1) {
-		gd->bd->bi_dram[1].start = SZ_4G;
-		gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
-	}
-}
-
 __weak int dram_init_banksize(void)
 {
 	if (CONFIG_IS_ENABLED(ARMADA_8K))
-		a8k_dram_init_banksize();
+		return a8k_dram_init_banksize();
 	else
-		fdtdec_setup_memory_banksize();
-
-	return 0;
+		return fdtdec_setup_memory_banksize();
 }
 
 __weak int dram_init(void)